Fixing a chip design error post-silicon in a semiconductor is like remarking a stone carving, as hardware modifications are significantly more challenging than fixing software issues. It comes with huge repair costs, revenue loss, resources loss, delays in time to market & compliance issues, etc. If undetected, these errors can lead to flawed chips being incorporated into electronic products, damaging the reputation of the chip design company and its partners, and impacting the end customer experience.
Errors are an inherent part of the innovation process. However, identifying and addressing errors early in chip design can minimize costs. To do this, the requirements management and verification teams must work in parallel during pre-silicon processes, including requirements design, verification planning & design, simulation, testing & redesign. Integrating verification and requirements management teams and their tools empowers teams to improve code coverage, detect errors early and make better decisions. The result is higher quality & accelerated innovation velocity.
We will demonstrate the integration between Cadence Verisium Manager (Formerly known as Cadence vManager), used by the verification team and Jama Connect, used by the requirements management team, and discuss how to achieve similar results with other requirements management solutions, such as DOORS & Jira.